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nt7501 33 x 100 ram-map lcd controller/driver 1v2.0 features ! direct ram data display using the display ram. when ram data bit is 0, it is not displayed. when ram data bit is 1, it is displayed. (in normal display mode) ! ram capacity: 65 x 132 = 8580 bits ! many command functions: read/write display data, display on/off, normal/reverse display, page address set, set display start line, set lcd bias, electronic contrast controls, read modify write, select segment driver direction and power save ! high-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800 ! serial interface ! single supply operation, 2.4 - 3.5v ! maximum 9v lcd driving output voltage ! 2x / 3x / 4x on chip dc-dc converter ! voltage regulator ! voltage follower (lcd bias: 1/5 or 1/6) ! on chip oscillator general description the nt7501 is a single-chip lcd driver for dot-matrix liquid crystal displays, which is directly connectable to a microcomputer bus. it accepts 8-bit serial or parallel display data directly sent from a microcomputer and stores it in an on-chip display ram. it generates a lcd drive signal independent of the microprocessor clock. the set of the on-chip display ram of 65 x 132 bits, and a one-to-one correspondence between the lcd panel pixel dots and the on-chip ram bits, permits implementation of displays with a high degree of freedom. as a total of 133 circuits of common and segment outputs are incorporated, a single chip of nt7501 can make 33 x 100 dots displays. no external operation clock is required for ram read/write operations. accordingly, this driver can be operated with minimum current consumption and its on-board low-current- consumption liquid crystal power supply can implement a high-performance handy display system with minimal current consumption and a minute lsi configuration.
nt7501 2 pad configuration 198 200 212 214 98 114 197 181 64 80 117 180~113 94~82 18~63 211~199 81 83 97 95 nt7501
nt7501 3 block diagram segment driver common driver shift register com s power supply circuit display data latch 132*65-dot display data ram line address decoder i/o buffer circuit line counter initial display line register output status selector circuit column address decoder 8-bit column address counter 8-bit column address counter page address register display timing generator circuit bus holder command decoder bus holder oscillator microprocessor interface i/o buffer seg0 seg99 com0 com31 coms v 0 v2 v4 v1 v3 vss cap1+ cap1- cap2+ cap2- cap3+ v out v r frs fr cl dyo dof m/s vs1 cs2 a0 rd (e) wr ) w / r ( c86 p/s res 1 cs v dd d7 (si) d5 d4 d3 d2 d1 d0 d6 (scl) tps0 tps1
nt7501 4 pad description power supply pad no. symbol i/o description 20 - 26 v dd supply 2.4 - 3.5v power supply input. these pads must be connected to each other 35 - 42 v ss supply ground input. these pads must be connected to each other 63 - 64 65 - 66 67 - 68 69 - 70 71 - 72 v 0 v 1 v 2 v 3 v 4 supply lcd driver supply voltages. the voltage determined by the lcd cell is impedance-converted by a resistive driver or an operation amplifier for application. voltages should have the following relationship: v 0 v 1 v 2 v 3 v 4 v ss when the on-chip operating power circuit is on, the following voltages are given to v 1 to v 4 by the on-chip power circuit. voltage selection is performed by the set lcd bias command v1 v2 v3 v4 4/5v0, 5/6v0 3/5v0, 4/6v0 2/5v0, 2/6v0 1/5v0, 1/6v0 lcd driver supplies pad no. symbol i/o description 47 - 48 cap1- o capacitor 1- pad for internal dc/dc voltage converter 49 - 50 cap1+ o capacitor 1+ pad for internal dc/dc voltage converter 51 - 52 cap2- o capacitor 2- pad for internal dc/dc voltage converter 53 - 54 cap2+ o capacitor 2+ pad for internal dc/dc voltage converter 45 - 46 cap3+ o capacitor 3+ pad for internal dc/dc voltage converter 12, 61 - 62, 77 v dd supply used for pad option or to connect to power filter capacitor 9, 15, 59 - 60, 73 - 74 v ss supply used for pad option or to connect to power filter capacitor 43 - 44 v out o dc/dc voltage converter output 55 - 56 v 0 o connect to rb 57 - 58 v r i voltage adjustment pad. applies voltage between v 0 and v ss using a resistive divider 75 - 76 tps0, tps1 i selects the temperature coefficient of the reference voltage
nt7501 5 system bus connection terminals pad no. symbol i/o description 27 - 34 d0 - d7 (si) (scl) i/o this is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard mpu data bus. when the serial interface is selected (p/s = ?l?), then d7 serves as the serial data input terminal (si) and d6 serves as the serial clock input terminal (scl). at this time, d0 to d5 are set to high impedance. when the chi p select is inactive , d0 to d7 are set to hi g h im p edance. 16 a0 i this is connected to the least significant bit of the normal mpu address bus, and it determines whether the data bits are data or a command. a0 = ?h?: indicate that d0 to d7 are display data. a0 = ?l?: indicates that d0 to d7 are control data. 8 res i when res is set to ?l?, the settings are initialized. the reset operation is performed by the res signal level. 11 - 13 1 cs cs2 i this is the chip select signal. when 1 cs = ?l? and cs2 = ?h?, then the chip select becomes active and data/command i/o are enabled 18 rd (e) i when connected to an 8080 mpu, it is active low. this pad is connected to the rd signal of the 8080mpu, and the nt7501 data bus is in an output statue when this signal is ?l?. when connected to a 6800 series mpu, this is active high. this is used as an enable clock input of the 6800 series mpu. 17 wr ( w r ) i when connected to an 8080 mpu, this is active low. this terminal connects to the 8080 mpu wr signal . the signals on the data bus are latched at the rising edge of the wr signal. when connected to a 6800 series mpu: this is the read/write control signal input terminal. when w r = ?h?: read. when w r = ?l?: write. 14 c86 i this is the mpu interface switch terminal. c86 = ?h?: 6800 series mpu interface. c86 = ?l?: 8080 series mpu interface. 10 p/s i this is the parallel data input/serial data input switch terminal. p/s = ?h?: parallel data input. p/s = ?l?: serial data input. the following applies depending on the p/s status: p/s data/command data read/write serial clock "h" a0 d0 to d7 "l" a0 si (d7) write only scl (d6) rd wr when p/s = ?l?, d0 to d5 are hz. d0 to d5 may be ?h?, ?l? or open. rd (e) and wr ( w / r ) are fixed to either ?h? or ?l?. with serial data input, ram display data reading is not supported. 7m/si this terminal selects the master/slave operation for the nt7501 chips. master operation outputs the timing signals that are required for the lcd display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. 4 cl i/o this is the display clock input terminal. when the nt7501 chips are used in master/slave mode, the various cl terminals must be connected.
nt7501 6 system bus connection terminals (continue) pad no. symbol i/o description 2 fr i/o this is the liquid crystal alternating current signal i/o terminal. m/s = ?h?: output m/s = ?l?: input when the nt7501 chip is used in master/slave mode, the various fr terminals must be connected. 3dyoo common drive signal output. this output is enabled for only in master operation and connects to the common driver dio pad. it becomes hz in slave operation. 6 vs1 o internal power supply voltage monitor output. 5 dof i/o this is the liquid crystal display blanking control terminal. m/s = ?h?: output m/s = ?l?: input when the nt7501 chip is used in master/slave mode, the various dof terminals must be connected 1frso this is the output terminal for the static drive. this terminal is only enabled when the static indicator is on when in master operation mode, and is used in conjunction with the fr terminal. liquid crystal drive pads pad no. symbol i/o description 98 - 197 seg0 - 99 o segment signal output for lcd display 81 - 96, 198 - 213 com15 - 0 com16 - 31 o common signal output for lcd display 97, 214 coms o these are the com output terminals for the indicator. both terminals output the same signal. do not connect these terminals if they are not used. when in master/slave mode, the same signal is output by both master and slave. option pads pad no. symbol i/o description 78 - 80 op1 - op3 i internal pull high, no connection for user
nt7501 7 functional description microprocessor interface interface type selection the nt7501 can transfer data via 8-bit bi-directional data bus (d7 to d0) or via serial data input (si). when high or low is selected for the parity of the p/s pad, either 8-bit parallel data input or serial data input can be selected as shown in table 1. when serial data input is selected, the ram data cannot be read out. table 1. p/s type 1 cs cs2 a0 rd wr c86 d7 d6 d0 to d5 h parallel input 1 cs cs2 a0 rd wr c86 d7 d6 d0 to d5 l serial input 1 cs cs2 a0 - - - si scl (hz) ?-? must always be high or low parallel input when the nt7501 selects parallel input (p/s = high), the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the c86 pad to go high or low as shown in table 2. table 2. c86 type 1 cs cs2 a0 rd wr d0 to d7 h 6800 microprocessor bus 1 cs cs2 a0 e w r d0 to d7 l 8080 microprocessor bus 1 cs cs2 a0 rd rw d0 to d7 data bus signals the nt7501 identifies the data bus signal according to a0, e, w r ( rd , wr ) signals. table 3. common 6800 processor 8080 processor a0 ( w r ) rd wr function 1 1 0 1 reads display data 1 0 1 0 writes display data 0 1 0 1 reads status 0 0 1 0 writes control data in internal register. (command) serial interface (p/s is low) the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data input and serial clock input are enabled when 1 cs is low and cs2 is high (in chip select status). when the chip is not selected, the shift register and counter are reset. the serial data of d7, d6, d0 are read at d7 in this sequence when the serial clock (scl) goes high. they are converted into 8-bit parallel data and processed on rising edge of every eighth serial clock signal. the serial data input (si) is determined to be the display data when a0 is high, and the control data when a0 is low. a0 is rea d on the rising edge of every eighth clock signal. figure1 shows a timing chart of serial interface signals. the serial clock sign must be terminated correctly against terminatio n reflection and ambient noise. operation checkout on the actual machine is recommended.
nt7501 8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 12345 6 78 910 11 12 13 14 cs2 si scl a0 1 cs figure 1. chip select inputs the nt7501 has two chip select pads, 1 cs and cs2 can interface to a microprocessor when 1 cs is low and cs2 is high. when these pads are set to any other combination, d0 to d7 are high impedance and a0, e and w r inputs are disabled. when the serial input interface is selected. the shift register and counter are reset. access to display data ram and internal registers the nt7501 can perform a series of pipeline processes between the lsi?s using the bus holder of the internal data bus in order to match the operating frequency of the display ram and the internal registers with that of the microprocessor. for example, th e microprocessor reads data from the display ram in the first read (dummy) cycle, stores it in the bus holder and outputs it onto the system bus in the next data read cycle. also, the microprocessor temporarily stores display data in the bus holder, and stores it in the display ram until the next dat a write cycle starts. when viewed from the microprocessor, the nt7501 access speed greatly depends on the cycle time rather than the access time to the display ram (t acc ). it shows the data transfer speed to/from the microprocessor can increase. if the cycle time is inappropriate, the microprocessor can insert the nop instruction that is equivalent to the wait cycle setup. however, there is a restriction in the display ram read sequence. when an address is set, the specified address data is not output at the read instruction immediately following. instead, the address data is output only during second data read. a single dummy read must be inserted after the address setup and after write cycle (refer to figure2). n n n+1 n+2 data bus holder mpu internal timing incremented n n+1 n n+1 n+2 preset n set address n dummy read data read address n data read address n+1 n address preset read signal column address r/w e a0 figure 2.
nt7501 9 busy flag the busy flag is set when the nt7501 starts to operate. during operation, it accepts read status instruction only. the busy fla g signal is output at pad d7 when read status is issued. if the cycle time (t cyc ) is correct, the microprocessor need not check the flag before issuing a command. this can greatly improve the microprocessor performance. initial display line register when the display ram data is read, the display line, according to com0 (usually, the top line of screen), is determined using register data. the register is also used for screen scrolling and page switching. the set display start line command sets the 6-bit display start address in this register. the register data is preset on the li ne counter each time the fr signal status changes. the line counter is incremented by cl signal and it generates a line address to allow 132 bit. column address counter this is a 8 bit presettable counter that provides the column address to the display ram (refer to figure4). it is incremented b y 1 when a read/write command is entered. however, the counter is not incremented but locked if a non-existing address above 84h is specified. it is unlocked when a column address is set again. the column address counter is independent of the page address register. when the adc select command is issued to display an inverse display, the column address decoder inverts the relationship between the ram column address and the display segment output. page address register this is a 4-bit page address register that provides a page address to the display ram (refer to figure 4). the microprocessor issues set page address command to change the page and access to another page. page address 8 (d3 is high, but d2,d1 and d0 are low) is ram area dedicated to the indicator, and only display data d0 is valid. display data ram the display data ram stores pixel data for the lcd. it is a 65-column by 132-row (8-page by 8 bit + 1) addressable array. each pixel can be selected when the page and column addresses are specified. the time required to transfer data is very short because the microprocessor enters d0 to d7 corresponding to the lcd common lines as shown in figure 3. therefore, multiple nt7501?s can easily configure a large display having high flexibility with very little data transmission restriction. the microprocessor writes and reads data to/from the ram through the i/o buffer. as the lcd controller operates independently, data can be written into the ram at the same time as the data is being displayed, without causing the lcd to flicker. 1 0 1 0 1 d0 d1 d2 d3 d4 com0 com1 com2 com3 com4 display data ram display on lcd figure 3.
nt7501 10 relationship between display data ram and address (if initial display line is 21h) pa g e address data line address d0 00 d1 01 d2 02 d3 03 d4 04 d5 05 d6 06 d3,d2, d1,d0 0,0,0,0 d7 07 d0 08 d1 09 d2 0a d3 0b d4 0c d5 0d d6 0e 0,0,0,1 d7 page1 0f d0 10 d1 11 d2 12 d3 13 d4 14 d5 15 d6 16 0,0,1,0 d7 page2 17 d0 18 d1 19 d2 1a d3 1b d4 1c d5 1d d6 1e 0,0,1,1 d7 page3 1f d0 20 d1 21 d2 22 d3 23 d4 24 d5 25 d6 26 0,1,0,0 d7 page4 27 d0 28 d1 29 d2 2a d3 2b d4 2c d5 2d d6 2e 0,1,0,1 d7 page5 2f d0 30 d1 31 d2 32 d3 33 d4 34 d5 35 d6 36 0,1,1,0 d7 page6 37 d0 38 d1 39 d2 3a d3 3b d4 3c d5 3d d6 3e 0,1,1,1 d7 page7 3f 1 , 0 , 0 , 0d0 pa g e8 d0= ?0? 10 11 12 71 72 73 column address adc d0= ?1? 73 72 71 12 11 10 lcd out seg0 seg1 seg2 seg97 seg98 seg99 page0 com output com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 coms start figure 4.
nt7501 11 display timing generator this section explains how the display timing generator circuit operates. signal generation to line counter and display data latch circuit the display clock (cl) generates a clock to the line counter and a latch signal to the display data latch circuit. the line address of the display ram is generated in synchronization with the display clock. 100-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment lcd drive output pad. the display data is read to the lcd drive circuit completely independent of access to the display data ram from the microprocessor. lcd ac signal (fr) generation the display clock generates an lcd ac signal (fr). the fr causes the lcd drive circuit to generate a ac drive waveform. it generates a 2-frame ac drive waveform. when the nt7501 is operated in slave mode on the assumption of multi-chip, the fr pad and cl pad become input pads. common timing signal generation the display clock generates an internal common timing signal and a start signal (dyo) to the common driver. a display clock resulting from frequency division of an oscillation clock is output from the cl pad. when an ac signal (fr) is switched, a high pulse is output as a dyo output at the turning edge of the previous display clock. refer to figure 5. the dyo output is output only in master mode. when the nt7501 is used for multi-chip, the slave requires to receive the fr, cl, dof signals from the master. table 4 shows the fr, cl, dyo and dof status. table 4. model operation mode fr cl dyo dof master output output output output nt7501 slave input input hz input hz denotes a high-impedance status example of nt7501 1/33 duty (dual-frame ac driver waveforms) cl 28 6 33 32 29 30 31 32 33 2345 1 2345 1 fr dyo com0 com1 ram data segn v 0 v 1 v4 v ss v ss v 4 v 1 v 0 v ss v 3 v 2 v 0 figure 5.
nt7501 12 display data latch circuit this circuit temporarily stores (or latches) display data (during a single common signal period) when it is output from display ram to lcd panel driver circuit. this latch is controlled by display in normal/reverse display on/off and entire display on commands. these commands do not alter the data. lcd driver this is a multiplexer circuit consisting of 100 segment outputs to generate four-level lcd panel drive signals. the lcd panel drive voltage is generated by a specific combination of display data, a com scan signal, and a fr signal. figure 5 gives an example of seg and com output waveform. oscillator circuit this is an oscillator having a complete built-in type cr, and its output is used as the display timing signal source or as the clock for the voltage booster circuit of the lcd power supply. the oscillator circuit is available in master mode only. the oscillator signal is divided and output as a display clock at the cl pad. power supply circuit the power supply circuit generates voltage to drive the lcd panel at low power consumption, and is available in nt7501 master mode only. the power supply circuit consists of a voltage booster, a voltage regulator and a lcd drive voltage follower. the power supply circuit built into the nt7501 is set for a small-scale lcd panel and is inappropriate for a large-pixel panel and a large-display-capacity lcd panel using multiple chips. as the large lcd panel has the dropped display quality due to a large load capacity, it must use an external power source. the power circuit is controlled by the set power control command. this command sets a three-bit data in the power control register to select one of eight power circuit functions. the external power supply and part of the internal power circuit funct ions can be used simultaneously. the following explains how the set power control command works. [control by set power control command] d2 turns on when the voltage booster control bit goes high, and d2 turns off when this bit goes low. d1 turns on when the voltage regulator control bit goes high, and d1 turns off when this bit goes low. d0 turns on when the voltage follower control bit goes high, and d0 turns off when this bit goes low. [practical combination examples] status 1: to use only the internal power supply status 2: to use only the voltage regulator and voltage follower status 3: to use only the voltage follower, input the external voltage v 0 status 4: to use only an external power supply because the internal power supply does not operate d2 d1 d0 voltage booster voltage regulator voltage follower external voltage input voltage booster terminal voltage regulator terminal 1 1 1 1 on on on - used used 2 0 1 1 off on on vout open used 3 0 0 1 off off on v0 open open 4 0 0 0 off off off v0 to v4 open open * the voltage booster terminals are cap1+, cap1-, cap2+, cap2- and cap3+ * combinations other than those shown in the above table are possible but impractical.
nt7501 13 booster circuit if capacitors c1 are connected between cap1+ and cap1-, cap2+ and cap2-, or between cap1- and cap3+ and between v ss and v out , the potential between v dd and v ss is boosted by four times toward the positive side and it is output at v out . for triple boosting, remove only the capacitor between cap1- and cap3+ from the connection of the quadruple boosting operation and then short between cap3- and v out . the triple boosted voltage appears at v out (cap3+). for double boosting, remove only capacitor c1 between cap2+ and cap2- from the connection of triple boosting operation, open cap2- and short between cap2+, cap3+ and vout. the double boosted voltage is output at vout (cap3+, cap2+). for quadruple boosting, set a v dd voltage range so that the voltage at v out may not exceed the absolute maximum rating. as the booster circuit uses signals from the oscillator circuit, the oscillator circuit must be operative. 4x step-up voltage relationships 3x step-up voltage relationships 2x step-up voltage relationships cap3+ cap1- cap1+ nt7501 2x step-up voltage circuit 3x step-up voltage circuit 4x step-up voltage circuit v ss v out v dd = 2.4v v ss = 0v v dd = 3v v ss = 0v v out = 3 x v dd = 9v v dd2 = 3v v ss = 0v v out = 2 x v dd = 6v cap2- cap2+ c1 c1 cap3+ cap1- cap1+ nt7501 v ss v out cap2- cap2+ c1 c1 cap3+ cap1- cap1+ nt7501 v ss v out cap2- cap2+ c1 c1 c1 c1 c1
nt7501 14 voltage regulator circuit the function of the internal voltage regulator circuits is to determine the liquid crystal operating voltage v 0, by adjusting resistors r a and r b , within the range v 0 < v out . vout is the operating voltage of the operational amplifier circuits shown in figure 6. feedback gain control for initial lcd voltage. external resistors are connected between v 0 and v r , and between v r and v ss and these resistors are chosen to give the desired v 0 according to the following equation: v 0 = (1 + r b /r a ) x v reg + r b x i ref tps1 tps0 thermal gradient (% / c) vreg (v) 0 0 -0.05 (internal v reg used) 2.2 0 1 -0.2 (internal v reg used) 2.45 10 0 v dd 11 0 v dd voltage regulator using the electronic volume control function the electronic volume control function can adjust the intensity (brightness level) of the lcd screen by electronic control command. software controls the 32 voltage levels of v 0 . this yields the following equation: v 0 = (1+ r b /r a ) x v reg + r b x i ref where i ref = 0 to 6.5 a 40% depending on the 5-bit data set by the electronic control command. v reg r a v ss v out r b v 0 i ref figure 6.
nt7501 15 reference power supply circuit for driving lcd panel -when using all lcd power circuits (voltage converter regulator and follower) (in case of 3x boosting circuit) m/s vout c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c1 c1 c2 c2 c2 c2 c2 ra rb v dd v ss c1 when only using voltage follower m/s vout c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 c2 c2 c2 c2 external power supply v dd v ss -when not using voltage booster circuits m/s vout c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 c2 c2 c2 c2 ra rb external power supply v dd v ss when not using the internal lcd power supply circuits c2 c1 m/s vout c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 external power supply v dd v ss *value of external capacitance item value 1.0~4.7 0.47~1.0 f
nt7501 16 command sequence when built-in power supply is turned off to turn off the built-in power supply, follow the command sequence as shown below after setting the system to standby mode. static indicator on display off entire display on command adh command aeh command a5h built-in power off } power save command reset circuit when the res input goes low, this lsi is initialized. initialized status 1. display off 2. normal display 3. adc select: normal display (adc command d0 = low) 4. read modify write off 5. power control register (d2, d1, d0) = (0, 0, 0,) 6. register data clear in serial interface 7. lcd power supply bias ratio 1/6 8. static indicator: off 9. display start line register set at line 1 10. column address counter set at address0 11. page address register set at page 0 12. output status register (d3) = (0) 13. electronic control register set at 0 14. test command off as seen in figure 8 microprocessor interface (reference example). connect the res pad to the reset pin of the microprocessor and initialize the microprocessor at the same time. in case the nt7501 does not use the internal lcd power supply circuit, the res must be low when the external lcd power supply is turned on. when res goes low, each register is cleared and set to the above initialized status. however, it has no effect on the oscillator circuit and output pads (fr, cl, dyo, d0 to d7) the initialization by res pad signal is always required during power-on. if the control signal from the mpu is hz, an overcurrent may flow through the ic. a protection is required to prevent the hz signal at the input pads during power-on. be sure to initialize it by res pad when turning on the power supply. when the reset command is used, only parameters 8 to 14 in the above initialization are executed.
nt7501 17 v dd v 1 v 4 v ss v 2 fr com0 com1 com2 seg0 seg1 com0 ~ seg0 com0 ~ seg1 v ss v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v 2 v 0 v 3 v ss com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 v 3 v 0 v 2 v 1 -v 4 -v 1 -v 0 -v 3 v ss -v 2 v 4 v 3 v 0 v 2 v 1 -v 4 -v 1 -v 0 -v 3 v ss -v 2 v 4 figure 7.
nt7501 18 commands the nt7501 uses a combination of a0, rd (e) and wr ( w r ) signals to identify data bus signals. as the chip analyzes and executes each command using the internal timing clock only, (regardless of external clock) its processing speed is very high and its busy check is usually not required. the 8080 series microprocessor interface enters read status when a low pulse is input to the rd pad and write status when a low pulse is input to the wr pad. the 6800 series microprocessor interface enters read status when a high pulse is input to the w r pad and write status when a low pulse is input to this pad. when a high pulse is input to the e pad, the command is activated. (for timing, see ac characteristics.). accordingly, in the command explanation and command table, rd (e) becomes 1(high) when the 6800 series microprocessor interface reads the status of display data. this is an only different point from the 8080 series microprocessor interface. looking at the 8080 series, microprocessor interface example commands are explained below. when the serial interface is selected, input data in sequence starting from d7. command set 1. display on/off alternatively turns the display on and off. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010111d the display turns off when d goes low and it turns on when d goes high. 2. set display start line specifies the line address (refer to figure 4) to determine the initial display line, or com0. the ram display data becomes the top line of the lcd screen. it is followed by the higher number of lines in ascending order, corresponding to the duty cycle. when this command changes the line address, the smooth scrolling or page change takes place. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 1 a5a4a3a2a1a0 a5 a4 a3 a2 a1 a0 line address 000000 0 000001 1 000010 2 :: 111110 62 111111 63
nt7501 19 3. set page address specifies the page address where to load display ram data in the page address register. any ram data bit can be accessed when its page address and column address are specified. the display remains unchanged even when the page address is changed. page address 8 is the display ram area dedicated to the indicator and only d0 is valid for data change. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 1 a3a2a1a0 a3 a2 a1 a0 page address 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 4. set column address specifies the column address of the display ram. divide the column address into 4 higher bits and 4 lower bits. set each of them in succession. when the microprocessor repeatedly access the display ram, the column address counter is incremented during each access until address 132 is accessed. the page address is not changed during this time. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 higher bits 0 1 0 0 0 0 1 a7 a6 a5 a4 lower bits 0 1 0 0 0 0 0 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 :: 10000011 131
nt7501 20 5. read status a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 busy adc on/off reset 0 0 0 0 busy: when high, the nt7501 is busy due to either internal operation or being reset. any command is rejected until busy goes low. the busy check is not required if enough time is provided for each cycle. adc: indicates the relationship between ram column address and segment drivers. when low, the display is reversed and the column address ?100-n? corresponds to segment driver n. when high, the display is normal and column address corresponds to segment driver n. on/off: indicates whether the display is on or off. when it goes low the display turns on. when it goes high, the display turns off. this is the opposite of display on/off command reset: indicates that initialization is in progress due to res signal or by reset command. when low, the display is on. when high, the chip is being reset. 6. write display data write 8-bit data in the display ram. as the column address is incremented by 1 automatically after each writing, the microprocessor can continue to write data of multiple words. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data 7. read display data reads 8-bit data from the display ram area specified by the column address and page address. as the column address is incremented by 1 automatically after each reading, the microprocessor can continue to read data of multiple words. a single dummy reading is required immediately after the column address setup. refer to the display ram section of functional description for details. note that no display data can be read via the serial interface. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data 8. adc select changes the relationship between the ram column address and the segment driver. the order of the segment driver output pads can be reversed by the software. this allows flexible ic layout during the lcd module assembly. for details, refer to the column address section of figure4. when display data is written or read, the column address is incremented by 1 as shown in figure4. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010000d when d is low, the right rotation (normal direction) when d is high, the left rotation (reverse direction) 9. normal/ reverse display reverses the display on/off status without rewriting the contents of the display data ram. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010011d when d is low, the ram data is high, being lcd on potential (normal display) when d is high, the ram data is low, being lcd on potential (reverse display)
nt7501 21 10. entire display on forcibly turns the entire display on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this command has priority over the normal/reverse display command. when d is low, the normal display status is provided. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010010d when d is high, the entire display on status is provided. if the entire display on command is executed during the display off status, the lcd panel enters power save mode. refer to the power save section for details. 11. set lcd bias selects a bias ratio for the voltage required for driving the lcd. this command is enabled when the voltage follower in the power supply circuit operates. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010001d the potential v0 is resistively divided inside the ic to produce potentials v1, v2, v3 and v4 which are necessary to drive the lcd. the bias ratio can be selected using the lcd bias setting command. moreover, the potentials v1, v2, v3 and v4 are converted in the impedance and supplied to the lcd drive circuit. duty bias ratio of lcd power supply 1/33 1/5 bias or 1/6 bias 12. read-modify-write a pair of read-modify-write and end commands must always be used. once a read-modify-write is issued, the column address is not incremental by the read display data command but incremented by the write display data command only. it continues until the end command is issued. when the end command is issued, the column address returns to the address before the read-modify-write was issued. this can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or others. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 11100000 note: any command except read/write display data and set column address can be issued during read-modify- write mode.
nt7501 22 cursor display sequence set page address set column address read-modify-write dummy read read data write data completed? end yes no 13. end cancels the read-modify-write mode and returns the column address to the original address (when read-modify-write was issued.) a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 11101110 column address n n+1 n+2 n+3 n+m n read-modify-write mode is selected end return
nt7501 23 14. reset resets the initial display line register, column address counter, page address register, and output status selector circuit to their initial status. the reset command does not affect the contents of the display ram. refer to the reset circuit section of function description. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 11100010 the reset command cannot initialize the lcd power supply. only the reset signal to the res pad can initialize the supply. 15. output status select register applicable to the nt7501. when d is high or low, the scan direction of the com output pad is selectable. refer to the output status selector circuit in the function description for details. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1100d* ** d : selects the scan direction of com output pad d = 0: normal (com0 com31) d = 1: reverse (com31 com0) *: invalid bit 16. set power control selects one of eight power circuit functions using a 3-bit register. an external power supply and part of the on-chip power circuit can be used simultaneously. refer to the power supply circuit section of the function description for details. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 0 1 0 1 a2 a1 a0 when a0 goes low, the voltage follower turns off. when a0 goes high, it turns on when a1 goes low, the voltage regulator turns off. when a1 goes high, it turns on when a2 goes low, the voltage booster turns off. when a2 goes high, it turns on 17. set electronic control adjusts the contrast of the lcd panel display by changing the v0 lcd drive voltage that is output by the voltage regulator of the on-board power supply. this command selects one of the 32 v0 lcd drive voltages by storing data in the 5-bit register. the v0 voltage adjusting range should be determined depending on the external resistance. refer to the voltage regulator section of the function description for details. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 a4 a3 a2 a1 a0 a4 a3 a2 a1 a0 i v0 i 00000 low 00001 00010 : " 11101 11110 11111 high set register to (d4, d3, d2, d1, d1, d0) = (0, 0, 0, 0, 0) to suppress the electronic control function.
nt7501 24 18. static indicator this command turns on or off the static drive indicators. the indicator display is controlled by this command only, and it is not affected by the other display control commands. either the fr or frs terminal is connected to either of the static indicator lcd drive electrodes, and the remaining terminal is connected to another electrode. when the indicator is turned on, the static drive operates and the indicator blinks at an interval of approximately one second. this pattern separation between indicator electrodes and dynamic drive electrodes is recommended. a closer pattern may cause a lcd and electrode deterioration. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1010110d d 0: static indicator off 1: static indicator on 19. power save (compound command) when all displays are turned on during display off, the power save command is issued to greatly reduce the current consumption. if the static indicators are off, the power save command sleeps the system. if on, this command stands by the system. release the sleep mode using the power save off command (display on command or entire display off command). static indicator off static indicator on power save (display off and entire display on) (sleep mode) (standby mode) power save off (display on or entire displays off ) static indicator on (sleep mode released) (standby mode released) sleep mode this mode stops every operation of the lcd display system, and can reduce current consumption to a nearly static current value if no access is made from the microprocessor. the internal status in the sleep mode is as follows: (1) stops the oscillator circuit and lcd power supply circuit. (2) stops the lcd drive and outputs the v ss level as the segment/common driver output. (3) holds the display data and operation mode provided before the start of the sleep mode. (4) the mpu can access the built-in display ram. standby mode stops the operation of the duty lcd display system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. the on operation of the static drive system indicates that the nt7501 is in the standby mode. the internal status in the standby mode is as follows: (1) stops the lcd power supply circuit. (2) stops the lcd drive and outputs the v ss level as the segment/common driver output. however, the static drive system operates. (3) holds the display data and operation mode provided before the start of the standby mode. (4) the mpu can access to the built-in display ram. when the reset command is issued in the standby mode, the sleep mode is set.
nt7501 25 when the lcd drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to the floating or v ss level, prior to, or concurrently with causing the nt7501 to go into the sleep mode or standby mode. when an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to the floating or v ss level, prior to, or concurrently with causing the nt7501 series to go into the sleep mode or standby mode. 20. test command this is the dedicated ic chip test command. it must not be used for normal operation. if the test command is issued unconsciously, set the res input to low or issue the reset command to release the test mode. a0 e rd w r wr d7 d6 d5 d4 d3 d2 d1 d0 01 0 1111** ** *: invalid bit cautions: the nt7501 holds an operation status specified by each command. however, the internal operation status may be changed by a high level of ambient noise. consideration must be given to suppressing the noise on the package and system and to preventing ambient noise. to prevent spike noise, built-in software for periodical status refreshment is recommended. the test command can be inserted in an unexpected place. therefore it is recommended the user enter the test mode reset command f0h during the refresh sequence.
nt7501 26 code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0101010111d turns on the lcd panel when goes high, and turns it off when goes low (2) set display start line 0 1 0 0 1 display start address specifies the ram display line for com0 (3) set page address 0 1 0 1 0 1 1 page address sets the display ram page in the page address register (4) set column address 4 higher bits 0 1 0 0 0 0 1 higher column address sets the 4 higher bits of column address of the display ram in register (5) set column address 4 lower bits 0 1 0 0 0 0 0 lower column address sets the 4 lower bits of column address of the display ram in register (6) read status 0 0 1 status 0 0 0 0 reads the status information (7) write display data 1 1 0 write data writes data in the display ram (8) read display data 1 0 1 read data reads data from the display ram (9) adc select 0101010000d sets the normal relationship between the ram column address and the segment driver when low, but reverses the relationship when high (10) normal/reverse display 0101010011d normal display when low, but reverse display when high (11) entire display on/off 0101010010d selects normal display (0) or entire display on (1) (12) set lcd bias 0101010001d sets the lcd drive voltage bias ratio (13) read-modify-write 0101110000 0 increments the column address counter during each writing when high and during each reading when low (14) end 0101110111 0 releases the read-modify- write (15) reset 0 1 0 1 1 1 0 0 0 1 0 resets the internal functions (16) set output status register 0101100d* * * selects the com output scan direction. * invalid data (17) set power control 0 1 0 0 0 1 0 1 operation status selects the power circuit operation mode (18) set electronic control register 0 1 0 1 0 0 electronic control value sets the v0 output voltage to electronic control re g ister (19) set static indicator on/off 0101010110d set the static indicator on/off 0: off 1: on (20) power save ---------- - compound command of display off and entire displa y on (21) test command 0 1 0 1 1 1 1 * * * * ic test command. do not use! (22) test mode reset 0 1 0 1 1 1 1 0 0 0 0 command of test mode reset note: do not use any other command, or system malfunction may result.
nt7501 27 absolute maximum rating* dc supply voltage (v dd ) . . . . . . . .. . -0.3v to + 6.0v dc supply voltage (v out , v 0 ) . . . . . . -0.3v to + 10.5v input voltage . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v operating ambient temperature . . . -40 c to + 85 c storage temperature . . . . . . . . . .. -55 c to + 125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics dc characteristics (v ss = 0v, v dd = 2.4 - 3.5v t a = -40 to 85 c unless otherwise specified) symbol parameter min. typ. max. unit condition 2.4 3.5 v 2.4 3.0 v triple boosting v dd operating voltage 2.4 2.4 v quadruple boosting v out booster output voltage 6.0 9.0 v v 0 voltage regulator operation voltage 5.0 8.0 v v reg1 reference voltage 1 2.0 2.2 2.4 v t a = 25 c, tps1, tps0 = 0, 0 v reg2 reference voltage 2 2.25 2.45 2.65 v t a = 25 c, tps1, tps0 = 0, 1 i dd1 dynamic current consumption 1 -2235 a v dd = 3v, v 0 = 8v, built-in power supply off, display on, display data = checker and no access, t a = 25 c i dd2 dynamic current consumption 2 -4880 a 3x boosting, v dd = 3v, v 0 = 8v, built-in power supply on, display on, display data = checker and no access, t a = 25 c i sp sleep mode current consumption 0.01 1 a during sleep, t a = 25 c i sb standby mode current consumption 10 20 a during standby, t a = 25 c v ihc high-level input voltage 0.8 x v dd v dd v a0, d0 - d7, rd (e), wr ( w r ), cs , cs2, fr, m/s, c86, p/s and dof v ilc low-level input voltage v ss 0.2 x v dd v a0, d0 - d7, rd (e), wr ( w r ), cs , cs2, fr, m/s, c86, p/s and dof v ohc high-level output voltage 0.8 x v dd v dd v i oh = -0.5ma (d0 ? d7, fr, frs, dyo, dof and cl) v olc low -level output voltage v ss 0.2 x v dd i ol = 0.5ma (d0 ? d7, fr, frs, dyo, dof and cl) v ihs high-level input voltage 0.85 x v dd v dd v schmitt trigger input (cl, scl(d6), tps0, tps1 and res ) v ils low-level input voltage v ss 0.15 x v dd v schmitt trigger input (cl, scl(d6), tps0, tps1 and res )
nt7501 28 dc characteristics (continued) symbol parameter min. typ. max. unit condition i li input leakage current -1.0 1.0 a v in =v dd or v ss (a0, rd (e), wr ( w r ), cs , cs2, m/s, c86, p/s, tps0, tps1 and res ) i hz hz leakage current -3.0 3.0 a when the d0 - d7, fr, cl, dyo and dof are in high impedance r on lcd driver on resistance 3.0 4.5 k ? v 0 = 8.0v t a = 25 c, these are the resistance values for when 0.1v voltage is applied between the output terminal segn or comn and the various power supply terminals (v1, v2, v3, v4) c in input pad capacity 5.0 8.0 pf t a = 25 c, f = 1mhz f osc oscillation frequency 18 22 26 khz t a = 25 c, v dd = 3.0v notes: 1. voltages v 0 v 1 v 2 v 3 v 4 v ss must always be satisfied.
nt7501 29 ac characteristics (1) system buses t as8 t ah8 t cyc8 t cclw t cclr t cchw t cchr t ds8 t ds8 t acc8 t ch8 a0 d0 - d7 (write) d0 - d7 (read) rd , wr 1 cs (cs2 = "1") (v dd = 2.4 - 3.5v, t a = -40 - 85 c) symbol parameter min. typ. max. unit condition t ah8 address hold time 0 ns t as8 address setup time 0 ns t cyc8 system cycle time 400 ns t cclw control l pulse width (wr) 55 ns t cclr control l pulse width (rd) 125 ns t cchw control h pulse width (wr) 180 ns t cchr control h pulse width (rd) 130 ns t ds8 data setup time 35 ns t dh8 data hold time 13 ns t acc8 rd access time 125 ns c l = 100pf t ch8 output disable time 10 90 ns c l = 100pf
nt7501 30 (2) system buses t as6 t ah6 t cyc6 t ds6 t dh6 t acc6 t oh6 a0 d0 - d7 (write) d0 - d7 (read) cs (cs2 = "1") e w / r t ewhw t ewhr t ewlw t ewlr (v dd = 2.4 - 3.5v, t a = -40 - 85 c) symbol parameter min. typ. max. unit condition t cyc6 system cycle time 400 ns t as6 address setup time 0 ns t ah6 address hold time 0 ns t ds6 data setup time 35 ns t dh6 data hold time 13 ns t oh6 output disable time 10 90 ns c l = 100pf t acc6 access time 125 ns c l = 100pf t ewlr 125 ns t ewlw enable low pulse width 55 ns t ewhr 125 ns t ewhw enable high pulse width 180 ns
nt7501 31 (3) serial interface t sas t sah t sds t sdh t css t csh t scyc t slw t shw tr tf a0 1 cs (cs2 = "1") scl si (v dd = 2.4 - 3.5v, t a = -40 - 85 c) symbol parameter min. typ. max. unit condition t scyc serial clock cycle 450 ns t shw serial clock h pulse width 180 ns t slw serial clock l pulse width 135 ns t sas address setup time 90 ns t sah address hold time 360 ns t sds data setup time 90 ns t sdh data hold time 90 ns t css 1 cs serial clock time 55 ns t csh 1 cs serial clock time 180 ns
nt7501 32 (4) display control timing cl (out) dyo t doh t dol t dfr fr (v dd = 2.4 - 3.5v, t a = -40 - 85 c) symbol parameter min. typ. max. unit condition t dfr fr delay time 13 70 ns c l = 50pf t doh dyo ?h? delay time 55 180 ns t dol dyo ?l? delay time 55 180 ns (5) reset timing t rw internal circuit status res t r during reset end of reset (v dd = 2.4 - 3.5v, t a = -40 - 85 c) symbol parameter min. typ. max. unit condition t r reset time 1.0 s t w reset low pulse width 1.0 s
nt7501 33 microprocessor interface (for reference only) 8080-series microprocessors v cc a0 a1 to a7 d0 to d7 gnd iorq wr res rd a0 d0 to d7 wr res rd 1 cs v ss c86 p/s decoder reset v ss v ss v dd mpu nt7501 v dd v dd cs2 6800-series microprocessors v cc a0 a1 to a15 d0 to d7 gnd a0 d0 to d7 2 cs w / r res e 1 cs v ss c86 p/s decoder reset v ss v dd mpu nt7501 v dd v dd vma w / r res e v dd figure 8
nt7501 34 bonding diagram 198 200 212 214 98 114 197 181 64 80 117 180~113 94~82 18~63 211~199 1450 m 81 83 97 95 7310 m nt7501 x y ( 0 , 0 ) pad no. designation x y pad no. designation x y 1 frs -3357.5 -655 31 d4 -807.5 -655 2 fr -3272.5 -655 32 d5 -722.5 -655 3 dyo -3187.5 -655 33 d6 -637.5 -655 4 cl -3102.5 -655 34 d7 -552.5 -655 5 dof -3017.5 -655 35 v ss -467.5 -655 6v s1 -2932.5 -655 36 v ss -382.5 -655 7 m/s -2847.5 -655 37 v ss -297.5 -655 8 res -2762.5 -655 38 v ss -212.5 -655 9v ss -2677.5 -655 39 v ss -127.5 -655 10 p/s -2592.5 -655 40 v ss -42.5 -655 11 1 cs -2507.5 -655 41 v ss 42.5 -655 12 v dd -2422.5 -655 42 v ss 127.5 -655 13 cs2 -2337.5 -655 43 v out 212.5 -655 14 c86 -2252.5 -655 44 v out 297.5 -655 15 v ss -2167.5 -655 45 cap3+ 382.5 -655 16 a0 -2082.5 -655 46 cap3+ 467.5 -655 17 wr -1997.5 -655 47 cap1- 552.5 -655 18 rd -1912.5 -655 48 cap1- 637.5 -655 19 v dd -1827.5 -655 49 cap1+ 722.5 -655 20 v dd -1742.5 -655 50 cap1+ 807.5 -655 21 v dd -1657.5 -655 51 cap2- 892.5 -655 22 v dd -1572.5 -655 52 cap2- 977.5 -655 23 v dd -1487.5 -655 53 cap2+ 1062.5 -655 24 v dd -1402.5 -655 54 cap2+ 1147.5 -655 25 v dd -1317.5 -655 55 v 0 1232.5 -655 26 v dd -1232.5 -655 56 v 0 1317.5 -655 27 d0 -1147.5 -655 57 v r 1402.5 -655 28 d1 -1062.5 -655 58 v r 1487.5 -655 29 d2 -977.5 -655 59 v ss 1572.5 -655 30 d3 -892.5 -655 60 v ss 1657.5 -655
nt7501 35 bonding diagram (continued) pad no. designation x y pad no. designation x y 61 v dd 1742.5 -655 101 seg3 3255 655 62 v dd 1827.5 -655 102 seg4 3185 655 63 v 0 1912.5 -655 103 seg5 3115 655 64 v 0 1997.5 -655 104 seg6 3045 655 65 v 1 2082.5 -655 105 seg7 2975 655 66 v 1 2167.5 -655 106 seg8 2905 655 67 v 2 2252.5 -655 107 seg9 2835 655 68 v 2 2337.5 -655 108 seg10 2765 655 69 v 3 2422.5 -655 109 seg11 2695 655 70 v 3 2507.5 -655 110 seg12 2625 655 71 v 4 2592.5 -655 111 seg13 2555 655 72 v 4 2677.5 -655 112 seg14 2485 655 73 v ss 2762.5 -655 113 seg15 2415 655 74 v ss 2847.5 -655 114 seg16 2345 655 75 tps0 2932.5 -655 115 seg17 2275 655 76 tps1 3017.5 -655 116 seg18 2205 655 77 v dd 3102.5 -655 117 seg19 2135 655 78 op1 3187.5 -655 118 seg20 2065 655 79 op2 3272.5 -655 119 seg21 1995 655 80 op3 3357.5 -655 120 seg22 1925 655 81 com15 3590 -648.1 121 seg23 1855 655 82 com14 3590 -578.1 122 seg24 1785 655 83 com13 3590 -508.1 123 seg25 1715 655 84 com12 3590 -438.1 124 seg26 1645 655 85 com11 3590 -368.1 125 seg27 1575 655 86 com10 3590 -298.1 126 seg28 1505 655 87 com9 3590 -228.1 127 seg29 1435 655 88 com8 3590 -158.1 128 seg30 1365 655 89 com7 3590 -88.1 129 seg31 1295 655 90 com6 3590 -18.1 130 seg32 1225 655 91 com5 3590 51.9 131 seg33 1155 655 92 com4 3590 121.9 132 seg34 1085 655 93 com3 3590 191.9 133 seg35 1015 655 94 com2 3590 261.9 134 seg36 945 655 95 com1 3590 331.9 135 seg37 875 655 96 com0 3590 401.9 136 seg38 805 655 97 coms 3590 471.9 137 seg39 735 655 98 seg0 3465 655 139 seg40 665 655 99 seg1 3395 655 139 seg41 595 655 100 seg2 3325 655 140 seg42 525 655
nt7501 36 bonding diagram (continued) pad no. designation x y pad no. designation x y 141 seg43 455 655 179 seg81 -2205 655 142 seg44 385 655 180 seg82 -2275 655 143 seg45 315 655 181 seg83 -2345 655 144 seg46 245 655 182 seg84 -2415 655 145 seg47 175 655 183 seg85 -2485 655 146 seg48 105 655 184 seg86 -2555 655 147 seg49 35 655 185 seg87 -2625 655 148 seg50 -35 655 186 seg88 -2695 655 149 seg51 -105 655 187 seg89 -2765 655 150 seg52 -175 655 188 seg90 -2835 655 151 seg53 -245 655 189 seg91 -2905 655 152 seg54 -315 655 190 seg92 -2975 655 153 seg55 -385 655 191 seg93 -3045 655 154 seg56 -455 655 192 seg94 -3115 655 155 seg57 -525 655 193 seg95 -3185 655 156 seg58 -595 655 194 seg96 -3255 655 157 seg59 -665 655 195 seg97 -3325 655 158 seg60 -735 655 196 seg98 -3395 655 159 seg61 -805 655 197 seg99 -3465 655 160 seg62 -875 655 198 com16 -3590 471.9 161 seg63 -945 655 199 com17 -3590 401.9 162 seg64 -1015 655 200 com18 -3590 331.9 163 seg65 -1085 655 201 com19 -3590 261.9 164 seg66 -1155 655 202 com20 -3590 191.9 165 seg67 -1225 655 203 com21 -3590 121.9 166 seg68 -1295 655 204 com22 -3590 51.9 167 seg69 -1365 655 205 com23 -3590 -18.1 168 seg70 -1435 655 206 com24 -3590 -88.1 169 seg71 -1505 655 207 com25 -3590 -158.1 170 seg72 -1575 655 208 com26 -3590 -228.1 171 seg73 -1645 655 209 com27 -3590 -298.1 172 seg74 -1715 655 210 com28 -3590 -368.1 173 seg75 -1785 655 211 com29 -3590 -438.1 174 seg76 -1855 655 212 com30 -3590 -508.1 175 seg77 -1925 655 213 com31 -3590 -578.1 176 seg78 -1995 655 214 coms -3590 -648.1 177 seg79 -2065 655 178 seg80 -2135 655
nt7501 37 package information nt7501 m c5 c5 a1 b3 a1 m n n 100 n m 80 n m 79 b2 99 a2 17 m n m n 17 m n m n r r b4 b4 c1 c4 c2 c1 c4 c2 b1 b1 b3 16 c3 16 c3 chip outline dimensions unit: m symbol dimensions in m symbol dimensions in m a1 169 b1 276.5 a2 70 b2 85 c1 232.1 b3 30 c2 120 b4 20 c3 70 m 90 c4 55.9 n 42 c5 25 r 35
nt7501 38 ordering information part no. package NT7501H-BDT au bump on chip tray

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